Minecraft mod · redstone CAD

LogicLoom

Write logic in Verilog, synthesize it with Yosys, and let LogicLoom place and route it as a working redstone circuit

Verilog → Yosys netlist Force-directed placement FLUTE + Lee routing Custom cell libraries

What it does

LogicLoom takes a synthesized logic design and automatically builds it out of redstone dust, repeaters, and torches in-game. Instead of hand-wiring gates block by block, you describe your circuit once in Verilog and let the mod handle placement and routing for you. It's much like the way a real chip goes from RTL to a physical layout.

The pipeline

Three commands take a design from source code to placed, routed redstone.

01

Synthesize

Write your design in Verilog 2001 (or SystemVerilog via the yosys-slang plugin), then run it through the included Synth.ys script with Yosys to produce a JSON netlist.

yosys Synth.ys
02

Place

Load the netlist and place the cells. Global placement uses a force-directed solver over a clique-model graph of the circuit; a Tetris-style pass then legalizes any remaining overlaps.

/logicloom load_json FILE_PATH /logicloom place
03

Route

Wires are routed automatically, choosing the shortest layer and path for every connection while working around obstacles.

/logicloom route

Under the hood

Placement

The circuit's hypergraph is converted into a graph using a clique model, where each connection is weighted by 2/n across n nodes.

A matrix equation (Ax = f + c) is solved per axis every iteration, balancing a spreading force against the pull of fixed points, until cells stop overlapping or the iteration limit is hit.

Routing

Multi-fanout nets are routed with the FLUTE algorithm, building a minimal rectilinear Steiner tree for each one.

Where a straight run is blocked, a Dijkstra-equivalent wave-propagation router finds a path around obstacles, trying each redstone Y-level from the bottom up before moving to the next.

Source, setup instructions, and the full command reference live on GitHub.

View the repository