RISC-V CPU
A minimal RV64IMA RISC-V CPU, built from scratch, capable of booting Linux all the way into an interactive BusyBox shell. I built this to understand the full stack from instruction decode up through virtual memory and interrupt handling
Architecture
- ISA
- RV64IMA (base integer, multiply/divide, atomics)
- Pipeline
- In-order, single-issue
- Virtual memory
- Sv39 paging with a direct-mapped, 512-entry TLB
- I/O
- 16550A-compatible UART for serial console
- Timers
- Barebones SiFive CLINT
- External Interrupts
- SiFive alike PLIC
Running Linux
The CPU boots a custom buildroot Linux kernel with a BusyBox root filesystem to a working shell prompt. The devicetree is passed down from OpenSBI
Challenges
- Getting Timer/External Interrupts fully working
- Making sure all MUL/DIV/REM edge cases are fully covered
Built With
- Written in SystemVerilog
- Simulated with Verilator
- Tested against riscv-arch-test